Direct Digital Frequency Synthesizer (DDFS) with Phase Selectable Interpolator

Direct Digital Frequency Synthesizer (DDFS) with Phase Selectable Interpolator

Docket: UAH-P-07008


UAH researchers have developed a DDFS device with less complexity and higher sinusoidal signal quality than is currently available. Numerical simplifications and processing algorithms are used to optimize performance while minimizing the number of processing elements. The phase signal produced by the accumulator of the DDFS is compared with a threshold value, and based on this comparison the appropriate interpolation polynomial is selected. This in turn processes the phase signal and generates the sinusoidal output. As a result, a reduced complexity digital circuit has been engineered with a higher quality sinusoidal signal. A significant improvement in the DDFS has also been achieved.

Below is a comparison between the fastest available commercial Spurious Free Dynamic Range (SFDR) chip available (Analog Devices’ AD9858) and the UAH invented DDFS device:

  Fastest available SFDR device UAH invention
Max. Clock Frequency 1 GHz 1 GHz:
Signal Quality (SFDR) 60 dBc 63.2 dBc
Complexity (Pipeline Stages): 82 4


  • Mobile communication devices where longer battery life is needed (i.e. cell phones, Bluetooth devices)
  • Radar systems
  • Satellite electronics
  • VLSI


  • Higher quality sinusoidal signal
  • Decreased power demand
  • Reduced complexity
  • No degradation in speed
  • Cost effective
  • Smaller size of the integrated circuit


  • State of Development: Prototype
  • Licensing Status: Available for licensing
  • Patent Status: Patent pending